CAD for VLSI Design I

By
Kamakoti, V. ; Balachandran, S. (Shankar)
(2014-01)

Presentation Slides

Topics : Evolution of CAD Tools; Importance of Design Automation; Basic Transistor Fundamentals; Gate Level Modeling; Higher Levels of Modeling; Types of CAD Tools; Verilog Quick Starter; Introduction to Simulators; Verilog Syntax; Verilog - Operators and expressions; Hierarchical Design and methodology; Delay modeling; Delay Modeling (contd); Blocking and Non Blocking Assignments; Behavioural Modeling; Verilog Tasks and Functions; Memory Modeling; Advanced Delay Modeling; Advanced Delay Modeling (Contd); Verilog Tricks; Introduction to Logic Synthesis; Logic Synthesis (Contd); Logic Synthesis (Contd); Synthesis: Assignment Statements; Synthesis: Arithmetic Operators; Synthesis: Bit Selects; Synthesis: Conditional Statements; Synthesis: Case Statements; Synthesis: Case Statements (Contd); Synthesis: Loops; Synthesis: Local & Integer Variables; Synthesis: Flip Flops with preset / clear; Synthesis: Blocking Vs Non Blocking Assignments; Synthesis: Unknowns and High Impedance; Optimization in Synthesis; Optimization in Synthesis (Contd); Introduction to Reconfigurable Computing; Introduction to FPGAs; Introduction to FPGAs (Contd); The Altera Quartus Flow; Lab Exercise; Project - 8279 Display and Keyboard Controller; Project - USART; Project - Hough Transform; You may also post on the forum Detailled Syllabus Unit 1: Introduction to CAD tools-Evolution of Design Automation-Basic Transistor Fundamentals-CMOS realizations of basic gates.(3 lectures) Unit 2: Modeling techniques, Types of CAD tools and Introduction to logic simulation(5 lectures) Unit 3: Verilog: Syntax, Hierarchical modeling and Delay modeling, Verilog constructs, Memory modeling (12 lectures) Unit 4: Logic Synthesis: Introduction synthesis of dirrerent verilog constructs(16 lectures) Unit 5: Introduction to Reconfigurable computing, FPGAs, the Altra Quartus II flow (4 lectures)

Published by:

National Programme on Technology Enhanced Learning (NPTEL)

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