Please use this identifier to cite or link to this item: http://doer.col.org/handle/123456789/23
Title: CAD for VLSI Design II
Authors: Kamakoti, V.
Balachandran, S. (Shankar)
Keywords: electronics & microelectronics
computer engineering
Edutags: Full Course
Undergraduate
Issue Date: 2000
Publisher: National Programme on Technology Enhanced Learning (NPTEL)
Abstract: Chapter 1 Transistor Theory - Chapter 2 Introduction to MOSFET - Chapter 3 CMOS Transistor Fundamentals - Chapter 4 Transistor Theory (Contd) - Chapter 5 CMOS Transistor Theory - Delay Issues - Chapter 6 CMOS Transistor Theory - Delay Issues (Contd) - Chapter 7 CMOS Transistor Theory - Delay Models - Chapter 8 Delay Elements in CMOS Circuits - Chapter 9 Delay Elements in CMOS Circuits (Contd) - Chapter 10 Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis - Chapter 11 Synthesis - Chapter 12 Synthesis - Synthesizable and Non Synthesizable constructs - Chapter 13 Synthesis - Logic Optimization, Resource Sharing - Chapter 14 Synthesis - Logic Optimization, Resource Sharing (Contd) - Chapter 15 Flip Flop and Latch optimaztion - Chapter 16 Introduction to Logical Effort - Chapter 17 Multistage Logic Networks - Chapter 18 Logical effort - Optimizing performance - Chapter 19 Logical Effort and Gain based Synthesis - Chapter 20 Logical Effort and Gain based Synthesis (Contd) - MAGMA Tutorial MAGMA ASIC Design Flow Stage 1 - MAGMA ASIC Design Flow Stage 2 - MAGMA ASIC Design Flow Stage 3 - Project - Superscalar Processor Implementation. Publication date is unknown.
Original Source: http://nptel.ac.in/courses/106106089/
Appears in Collections:Engineering

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